LS3C6000
LS3C6000
Loongson 3C6000 series processors adopt Loongson's 4th-generation microprocessor architecture, integrating 16 LA664 cores on a single die with support for 32 logical cores via simultaneous multi-threading technology. Based on the Loongson Coherent Link, the 3C6000 series supports three packaging configurations with varying numbers of dies (S/D/Q). Through board-level multi-path direct connections, it can scale up to 256 logical cores, delivering substantial computing power for diverse application scenarios. This effectively meets user demands for both single-core high performance and multi-core high concurrency requirements.
LS3C6000 Specification
Frequency
2.0GHz - 2.2GHz
Floating-point double-precision peak computing speed
[email protected](S), [email protected]（D）, [email protected](Q)
Physical cores
16(S), 32(D), 64(Q)
Logical cores
32(S), 64(D), 128(Q)
Processor core
64-bit superscalar LA664 cores; Supports the LoongArch? ISA; Supports 128/256-bit vector instructions; 6-issue out-of-order execution; 4 fixed-point units, 4 vector units and 4 memory access units
High-speed cache
Each processor core contains a 64KB private L1 instruction cache and a 64 KB private L1 data cache; Each processor core contains a 256KB private L2 cache; Each die features a shared 32MB L3 cache
Memory controller
4×72-bit DDR4-3200 controller(S), 8×72-bit DDR4-3200 controller(D/Q)
High-speed I/O
4-channel PCIe×16 interfaces , 64 lanes total(S), 8-channel PCIe×16 interfaces, 128 lanes total(D/Q )
Die-to-die interconnect
Loongson Coherent Link, multiplexable PCIe
Other I/O
SPI, UART, I2C, GPIO
Security module
Loongson SE, integrates LA264 processor core, supports SM2/SM3/SM4
Multi-die interconnect
2–4 die interconnect
Power management
Supports dynamic shutdown of the clocks of main modules; Supports dynamic frequency scaling in main clock domains; Supports dynamic voltage scaling in main voltage domains
Typical power consumption
100W-120W（S）, 180W-200W（D）, 250W-300W（Q）
