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            ISA: LoongArch

            LS3A5000 Specification

            Key Features

            - Loongson instruction set architecture (LoongArch? ) 
            - Measured single-core in SPEC CPU 2006 Base result over 26
            - Measured memory bandwidth over 25 GB/s with DDR4-3200 interface
            - Unified ecosystem compatibility: real-time binary translation supports of applications from different ISAs
            - Fine-grained power management: Built-in power control core for dynamic voltage and frequency scaling


            Frequency

            2.3GHz–2.5GHz

            Peak computing speed

            160GFLOPS

            Processor core

            based on LoongArch; supporting 128/256-bit vector instructions; 4-issue out-of-order execution; 4 fixed-point units, 2 vector units, and 2 memory access units

            High-speed cache

            Each processor core contains a 64KB private L1 instruction cache and a 64KB private L1 data cache. Each processor core contains a 256KB private L2 cache. All processor cores share a 16MB L3 cache.

            Memory controller

            Two 72-bit DDR4-3200 controllers; supporting ECC

            High-Speed I/O

            two HyperTransport 3.0 controllers; supporting CC-NUMA

            Other I/O

            1 SPI, 1 UART, 2 I2Cs, and 16 GPIO interfaces

            Power management

            supporting dynamic shutdown of the clocks of main modules; supporting dynamic frequency scaling in main clock domains; supporting dynamic voltage scaling in main voltage domains

            Typical power Consumption

            [email protected]

            LS3A5000 Manual

            LS3A5000 Application

            PC
            Server
            CoreSwitch
            VPN
            Data Gateway
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